Advanced processes and techniques may be employed in design and fabrication of IC devices, particularly to aid with reducing the geometries of components and structures utilized to scale down IC devices beyond 10 nm. Scaling IC devices requires improvements in power, performance, and density. Improvement in performance may require transport in ballistic regime, full quantization of the channel, and sub 10 nm nanowires with gate all round structures for full quantization. Scaling beyond 10 nm would require non-planar NW structures to meet density requirements. However, such scaling would require integrated devices on a NW having alternate channel materials to meet the power-performance requirements.
A need therefore exists for a methodology for forming a NW with multiple devices having alternate channel materials and the resulting device.